The present invention relates to a semiconductor memory device, and more particularly to a data output control circuit for controlling a data output timing for outputting data in synchronization with a system clock in response to an external command input to the semiconductor memory device.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as a data storage. The semiconductor memory device outputs data according to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into memory cells selected by the addresses.
As the operating speed of the system increases and semiconductor integrated circuit technologies are advanced, semiconductor memory devices are required to input and output data at higher speed. More particularly, a synchronous semiconductor memory device has been developed which may input/output data in synchronization with an input system clock in order to input/output the data at high speed. However, since the synchronous semiconductor memory device was not enough to satisfy a required data input/output speed, a double data rate (DDR) synchronous semiconductor memory device has been developed which inputs/outputs data in synchronization with a rising edge and a falling edge of a system clock, respectively.
Since the DDR synchronous semiconductor memory device inputs/outputs data at both the rising edge and falling edge of the system clock, it must process two data during one cycle of the system clock. That is, the DDR synchronous semiconductor memory device must output stored data at the rising edge or falling edge of the system clock, and receive and store data at the rising edge or falling edge of the system clock. Specifically, a data output timing of the DDR synchronous semiconductor memory device must be exactly synchronized with the rising edge or falling edge of the system clock. To this end, DDR synchronous semiconductor memory device is provided with a data output circuit for outputting data at the rising edge and falling edge of the input system clock.
The semiconductor memory device must output data in response to a read command when a predetermined cycles of the system clock pass by after the corresponding read command is input thereto. A column address strobe (CAS) latency (CL) determines a start timing of data output. Generally, the semiconductor memory device supports a plurality of CAS latencies, which may be adjusted according to operation environment. The CAS latency is set in a mode register set (MRS) of the semiconductor memory device. When the external read command is input, the semiconductor memory device determines a data output timing according to the CAS latency set in the MRS.
The system clock input to the semiconductor memory device is delayed by a clock input buffer, which buffers the system clock to output an internal clock, and a transmission line for transferring the internal clock signal. The delayed system clock is then transferred to the data output circuit. If data are output in synchronization with the delayed system clock, an external device will receive data which are not synchronized with the rising edge and falling edge of the system clock. To solve this problem, the semiconductor memory device includes a delay locked loop (DLL) for locking a delay of a clock signal. The DLL is a circuit for compensating the system clock for a delay value that is caused by an internal circuit of the semiconductor memory device until the system clock is input to the semiconductor memory device and thereafter is transferred to the data output circuit.
In order to output data in response to an external command exactly after the CAS latency, the semiconductor memory device includes a data output control circuit which determines a data output timing using a delay locked clock output from the delay locked loop and the CAS latency set in the MRS. If the delay locked clock with a locked phase is output and then its phase is not changed anymore in spite of a change of an operation mode or environment of the semiconductor memory device, the delay locked loop stops a delay-locking operation for reducing power consumption. In this case, the data output control circuit, however, may continuously output data using the delay locked clock with a locked phase.
FIG. 1 is a block diagram of a conventional semiconductor memory device. The semiconductor memory device outputs data in synchronization with a delay locked clock output from the delay locked loop or outputs data in synchronization with the external system clock when the delay locked loop does not perform the delay-locking operation.
Referring to FIG. 1, the semiconductor memory device includes a command decoder 110, a clock buffer 120, a delay locked loop (DLL) 130, an output signal generator 150, an output delay 170, and an output timing determiner 190. When the command decoder 110 receives and decodes an external command CMD and then recognizes the external command as a read command RDCMD, it outputs the read command RDCMD to the output signal generator 150. External system clocks CK and CKB are buffered by the clock buffer 120 and are transferred to the output signal generator 150 as an internal clock ICLK.
The output signal generator 150 receiving the internal clock ICLK generates an output enable signal OE having information on a burst length (BL) in response to the read command RDCMD. The delay locked loop 130 outputs a delay locked clock DLLCLK to the output delay 170 in response to the internal clock ICLK. The delay locked clock DLLCLK is generated after delay locking of the external system clocks CK and CKB by compensating a value delayed by an internal circuit of the semiconductor memory device until the external system clocks CK and CKB are input to the semiconductor memory device and are transferred to a data output circuit. When a DLL stop signal DLLOFF is activated, the delay locked loop 130 stops the delay-locking operation and passes the internal clock ICLK. The output delay 170 compensates a phase difference between the external system clock CK and the delay locked clock DLLCLK, and is commonly similar to a replica delay circuit for feedback included in the delay locked loop. Furthermore, the output delay 170 models a delay value of the external system clock CK delayed in the semiconductor memory device, and outputs a delayed delay-locked clock ECLK obtained by delaying the delay locked clock DLLCLK to the output timing determiner 190.
The output timing determiner 190 receives the output enable signal OE and the delayed delay-locked clock ECLK to output a data output control signal OUTEN corresponded to the CAS latency. More specifically, during an activation section of the output enable signal OE corresponded to the burst length (BL), the output timing determiner 190 shifts a phase of the delayed delay-locked clock ECLK according to the CAS latency to thereby generate the data output control signal OUTEN.
FIG. 2 a signal timing diagram illustrating the operation of the semiconductor memory device of FIG. 1 when the delay locked loop 130 is enabled.
Referring to FIG. 2, the DLL stop signal DLLOFF is deactivated to a logic low level, and the delay locked loop 130 performs the delay locking operation to output the delay locked clock DLLCLK. The delay locked clock DLLCLK is output by compensating a delay amount of the system clock CK in the semiconductor memory device, and a phase of the delay locked clock DLLCLK leads a phase of the corresponding system clock CK by a compensation time tAC. The output delay 170 delays the delay locked clock DLLCLK by a delay amount tDLL of the replica circuit to output the delayed delay-locked clock ECLK. The output enable signal OE output from the output signal generator 150 is activated in synchronization with the rising edge of the system clock CK in response to the read command RDCMD. At this point, an output signal generation time tOE extends from the rising edge of the system clock CK to an activation of the output enable signal OE.
When the rising edge of the delayed delay-locked clock ECLK occurs after an activation of the output enable signal OE, the output timing determiner 190 can output the data output control signal OUTEN at a desired time. That is, the output timing determiner 190 of the semiconductor memory device can have an operation margin tS shown in FIG. 2.
FIG. 3A is a signal timing diagram illustrating the operation of the semiconductor memory device shown in FIG. 1 in a low frequency operation environment when the delay locked loop is disabled. FIG. 3B is a signal timing diagram illustrating the operation of the semiconductor memory device shown in FIG. 1 in a high frequency operation environment when the delay locked loop is disabled.
Referring to FIG. 3A, when the DLL stop signal DLLOFF is activated to a logic high level, the delay locked loop 130 passes the internal clock ICLK without performing the delay-locking operation, to output the delay locked clock DLLCLK. Therefore, the delay locked clock DLLCLK is delayed by a pass time tICK from the rising edge of the system clock CK. At this point, the delay locked clock DLLCLK is delayed through the output delay 170 by a delay amount tDLL of the replica circuit, as described above with reference to FIG. 2.
In response to the read command RDCMD, the output signal generator 150 generates the output enable signal OE after the output signal generation time tOE elapses from the system clock CK (described by an arrow) corresponding to the read command RDCMD. Accordingly, the output time determiner 190 of the semiconductor memory device can have an operation margin tS shown in FIG. 3A.
Referring to FIG. 3B, similar to FIG. 3A, since the DLL stop signal DLLOFF is activated to a logic high level, the delay locked loop 130 outputs the delay locked clock DLLCLK which is delayed by a pass time tICK from the rising edge of the system clock CK. The output delay 170 delays the delay locked clock DLLCLK by a delay amount tDLL of the replica circuit to output the delayed delay-locked clock ECLK, as described above with reference to FIG. 2.
The output signal generator 150 generates the output enable signal OE after the output signal generation time tOE according to the read command RDCMD. In this case, the delayed delay-locked clock ECLK, which has the same period as the system clock CK and frequency higher than that of FIG. 3A, has twice the rising edges during a time corresponding to the delay amount tDLL of the replica circuit. Accordingly, the output timing determiner 190 of the semiconductor memory device recognizes a rising edge prior to the rising edge of the delayed delay-locked clock ECLK which is delayed as much time as the delay amount tDLL of the replica circuit, and outputs the data output control signal OUTEN after shifting a phase of the delayed delay-locked clock ECLK according to the CAS latency. In this case, malfunction may occur in the semiconductor memory device because a data output timing according to the data output control signal OUTEN becomes faster than a desired timing by one period 1tCK of the system clock CK.
In a high frequency operation environment, if tOE<tICK+tDLL−1tCK (where tOE is the output signal generation time tOE, tICK is the pass time tICK, tDLL is the delay amount of the replica circuit, and 1tCK is the period of the system clock CK), the data output timing become faster by the one period 1tCK of the system clock than the desired timing.
As described above, since the delay amount tDLL of the replica circuit of the output delay 170 has a constant value irrespective of a frequency of the system clock CK, the output timing of data, which are output after the read operation, is not adjusted according to the CAS latency when the semiconductor memory device operates in accordance with the system clock CK having a high frequency. In FIG. 3B, it has been described that the data are output according to a value of CL-1, which is one less than the CAS latency, instead of the CAS latency. However, when the system clock CK has higher frequency than in of FIG. 3, the data can be output according to a value of CL-2 or a value of CL-3, which is less than a value of CL-1. Ultimately, in an operation state where the delay locked loop 130 of the semiconductor memory device does not perform the delay locking operation, the data corresponded to the read command RDCMD may not be output according to the CAS latency.
Referring to FIGS. 3A and 3B, when tOE=tICK+tDLL−1tCK, the data are output according to the CAS latency or the value of CL-1, depending on operation environments (for example, process, voltage, and temperature) of the semiconductor memory device. Therefore, the operation reliability of the semiconductor memory device is greatly degraded.
Consequently, a frequency of the delay locked clock increases according to a high frequency of the system clock of the semiconductor memory device. On the other hand, when a delay amount of the output delay, which includes a replica delay element for compensating the delay locked clock for a delay amount delayed in the semiconductor memory device, is maintained to be same, the change of the data output timing may occur in the conventional semiconductor memory device which counts the rising edge of the system clock and the rising edge of the delay locked clock to determine the data output timing. Therefore, the conventional semiconductor memory device has difficulty in performing a high frequency operation.